{"id":214,"date":"2026-10-22T17:28:54","date_gmt":"2026-10-22T21:28:54","guid":{"rendered":"https:\/\/www.terryellsworth.com\/?p=214"},"modified":"2026-10-22T17:28:54","modified_gmt":"2026-10-22T21:28:54","slug":"a-new-cpu-architecture-aurora","status":"publish","type":"post","link":"https:\/\/www.terryellsworth.com\/?p=214","title":{"rendered":"A new CPU Architecture- AURORA"},"content":{"rendered":"\n

Of my four big software\/hardware projects, I have decided to build a new processor architecture. This is not a RISC architecture, but a hybrid architecture- a hybrid CISC-VLIW- full 64-bit data and address lines, and a 512-bit VLIW for packetization. It’s a two-ring (user\/supervisor) processor, where the instruction set will be open-source, without a single piece of legacy instructions or seeking backward compatibility at all.<\/p>\n\n\n\n

The 512-but packetization allows compiling several operations into one instruction for parallel processing, if the developer sees it as needed. This allows compilers written on AURORA the ability to make operations more efficient.

Here is the guide to the instruction set so far:<\/p>\n\n\n\n

AURORA v0.13 defines 32 scalar instructions, plus the optional 512-bit packet format that bundles those same instructions.<\/strong> I checked the source archive\u2019s ISA specification, assembler, decoder, and emulator. The reference below distinguishes the architectural rules from limitations in the current implementation.<\/p>\n\n\n\n

Machine model and instruction encoding<\/strong><\/p>\n\n\n\n

AURORA is a little-endian, byte-addressed architecture with 64-bit integer registers, addresses, and program counter.<\/p>\n\n\n\n

Component<\/th>Definition<\/th><\/tr><\/thead>
General-purpose registers<\/td>32 registers, R0<\/code>\u2013R31<\/code>, each 64 bits<\/td><\/tr>
Zero register<\/td>None; R0<\/code> is writable<\/td><\/tr>
Stack pointer<\/td>Conventionally R30<\/code>; remains an ordinary register<\/td><\/tr>
Link register<\/td>Conventionally R31<\/code>; CALL<\/code> and RET<\/code> explicitly use it<\/td><\/tr>
Program counter<\/td>64-bit PC<\/code><\/td><\/tr>
Arithmetic condition flags<\/td>No carry, zero, sign, or overflow flags defined<\/td><\/tr>
Scalar alignment<\/td>Instructions may start at any byte address<\/td><\/tr>
Scalar lengths<\/td>Currently 1, 3, 4, 5, or 10 bytes; packet slot lengths can represent 1\u201315<\/td><\/tr>
Packet alignment<\/td>Mandatory 64-byte alignment<\/td><\/tr>
Integer byte order<\/td>Little-endian, including instruction immediates<\/td><\/tr>
Privilege modes<\/td>User and Supervisor<\/td><\/tr>
Floating-point\/vector registers<\/td>Not defined in the current instruction set<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Each scalar instruction begins with a one-byte opcode. Each register operand occupies one byte: bits 4\u20130 select the register, and bits 7\u20135 must be zero.<\/p>\n\n\n\n

In the tables below, Rd<\/code> is a destination register, Rs<\/code> a source, and Ra<\/code>\/Rb<\/code> additional sources. Instruction lengths include the opcode byte. All opcode values are hexadecimal.<\/p>\n\n\n\n

Data movement \u2014 2 instructions<\/strong><\/p>\n\n\n\n

Opcode<\/th>Instruction<\/th>Bytes<\/th>Operation<\/th><\/tr><\/thead>
10<\/code><\/td>MOV Rd, Rs<\/code><\/td>3<\/td>Copy all 64 bits of Rs<\/code> into Rd<\/code>.<\/td><\/tr>
11<\/code><\/td>MOVI Rd, imm64<\/code><\/td>10<\/td>Load a full 64-bit immediate into Rd<\/code>.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n

Encodings:<\/p>\n\n\n\n

MOV:  opcode, destination, source\nMOVI: opcode, destination, immediate64<\/code><\/pre>\n\n\n\n
MOVI<\/code> can load an entire 64-bit constant or address in one instruction:<\/p>\n\n\n\n
MOVI R1, 0x123456789ABCDEF0\nMOV  R2, R1<\/code><\/pre>\n\n\n\n
There are no separate high-half\/low-half immediate instructions. The assembler supports symbol relocations for scalar MOVI<\/code>, allowing the linker to fill in a 64-bit address.<\/p>\n\n\n\n
Integer arithmetic and logic \u2014 8 instructions<\/strong><\/p>\n\n\n\n
Opcode<\/th>Instruction<\/th>Bytes<\/th>Operation<\/th><\/tr><\/thead>
20<\/code><\/td>ADD Rd, Ra, Rb<\/code><\/td>4<\/td>Rd = Ra + Rb<\/code>, modulo \\(2^{64}\\).<\/td><\/tr>
21<\/code><\/td>SUB Rd, Ra, Rb<\/code><\/td>4<\/td>Rd = Ra \u2212 Rb<\/code>, modulo \\(2^{64}\\).<\/td><\/tr>
22<\/code><\/td>AND Rd, Ra, Rb<\/code><\/td>4<\/td>Bitwise AND.<\/td><\/tr>
23<\/code><\/td>OR Rd, Ra, Rb<\/code><\/td>4<\/td>Bitwise OR.<\/td><\/tr>
24<\/code><\/td>XOR Rd, Ra, Rb<\/code><\/td>4<\/td>Bitwise exclusive OR.<\/td><\/tr>
25<\/code><\/td>MUL Rd, Ra, Rb<\/code><\/td>4<\/td>Low 64 bits of the product.<\/td><\/tr>
26<\/code><\/td>SHL Rd, Rs, imm8<\/code><\/td>4<\/td>Logical left shift by imm8 & 63<\/code>.<\/td><\/tr>
27<\/code><\/td>SHR Rd, Rs, imm8<\/code><\/td>4<\/td>Logical right shift by imm8 & 63<\/code>.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
The first six use this encoding:<\/p>\n\n\n\n
opcode, destination, source_a, source_b<\/code><\/pre>\n\n\n\n
The shifts use:<\/p>\n\n\n\n
opcode, destination, source, shift_immediate<\/code><\/pre>\n\n\n\n
Arithmetic wraps without setting flags or raising an integer-overflow exception. MUL<\/code> is specified as the low half of an unsigned product; the low 64-bit result also matches two\u2019s-complement signed multiplication.<\/p>\n\n\n\n
Both shifts introduce zero bits. SHR<\/code> is not<\/strong> an arithmetic, sign-preserving right shift. Shift counts are masked to six bits, so a count of 64 becomes zero.<\/p>\n\n\n\n
There are no immediate forms of ADD<\/code>, SUB<\/code>, or the bitwise operations. A constant must first be placed in a register:<\/p>\n\n\n\n
MOVI R2, 1\nADD  R1, R1, R2<\/code><\/pre>\n\n\n\n
Memory access \u2014 8 instructions<\/strong><\/p>\n\n\n\n
All memory instructions are five bytes long and use a base register plus a signed 16-bit byte displacement:\\[ \\text{address} = R_\\text{base} + \\operatorname{signExtend}(\\text{disp16}) \\]<\/p>\n\n\n\n
The displacement range is \u221232,768 through +32,767 bytes<\/strong>.<\/p>\n\n\n\n
Opcode<\/th>Instruction<\/th>Access width<\/th>Operation<\/th><\/tr><\/thead>
30<\/code><\/td>LD64 Rd, [Rb+disp16]<\/code><\/td>64 bits<\/td>Load a complete 64-bit value.<\/td><\/tr>
31<\/code><\/td>ST64 Rs, [Rb+disp16]<\/code><\/td>64 bits<\/td>Store a complete 64-bit value.<\/td><\/tr>
32<\/code><\/td>LD8U Rd, [Rb+disp16]<\/code><\/td>8 bits<\/td>Load a byte and zero-extend to 64 bits.<\/td><\/tr>
33<\/code><\/td>ST8 Rs, [Rb+disp16]<\/code><\/td>8 bits<\/td>Store the low 8 bits of Rs<\/code>.<\/td><\/tr>
34<\/code><\/td>LD16U Rd, [Rb+disp16]<\/code><\/td>16 bits<\/td>Load and zero-extend to 64 bits.<\/td><\/tr>
35<\/code><\/td>ST16 Rs, [Rb+disp16]<\/code><\/td>16 bits<\/td>Store the low 16 bits of Rs<\/code>.<\/td><\/tr>
36<\/code><\/td>LD32U Rd, [Rb+disp16]<\/code><\/td>32 bits<\/td>Load and zero-extend to 64 bits.<\/td><\/tr>
37<\/code><\/td>ST32 Rs, [Rb+disp16]<\/code><\/td>32 bits<\/td>Store the low 32 bits of Rs<\/code>.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
Their binary layout is:<\/p>\n\n\n\n
opcode, data_register, base_register, displacement16<\/code><\/pre>\n\n\n\n
Natural alignment is required:<\/p>\n\n\n\n
Width<\/th>Required address alignment<\/th><\/tr><\/thead>
8 bits<\/td>1 byte<\/td><\/tr>
16 bits<\/td>2 bytes<\/td><\/tr>
32 bits<\/td>4 bytes<\/td><\/tr>
64 bits<\/td>8 bytes<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
For example:<\/p>\n\n\n\n
LD64  R3, [R10+16]\nLD8U  R4, [R10+1]\nST32  R5, [R10+8]<\/code><\/pre>\n\n\n\n
The assembler also accepts memory-first store syntax, such as ST32 [R10+8], R5<\/code>.<\/p>\n\n\n\n
There are no signed narrow-load instructions, indexed\/scaled addressing modes, auto-increment addressing, or direct memory-to-memory moves. More elaborate address calculations use ordinary register arithmetic.<\/p>\n\n\n\n
Control flow \u2014 5 instructions<\/strong><\/p>\n\n\n\n
Opcode<\/th>Instruction<\/th>Bytes<\/th>Operation<\/th><\/tr><\/thead>
40<\/code><\/td>JMP rel32<\/code><\/td>5<\/td>Unconditional PC-relative jump.<\/td><\/tr>
41<\/code><\/td>BRZ Rs, rel16<\/code><\/td>4<\/td>Branch if the full 64-bit source register equals zero.<\/td><\/tr>
42<\/code><\/td>BRNZ Rs, rel16<\/code><\/td>4<\/td>Branch if the source register is nonzero.<\/td><\/tr>
43<\/code><\/td>CALL rel32<\/code><\/td>5<\/td>Save the following instruction\u2019s address in R31<\/code>, then branch.<\/td><\/tr>
44<\/code><\/td>RET<\/code><\/td>1<\/td>Set PC<\/code> to R31<\/code>.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
All relative offsets are measured from the first byte after the instruction<\/strong>:<\/p>\n\n\n\n
target = instruction_address + instruction_length + signed_offset<\/code><\/pre>\n\n\n\n
JMP<\/code> and CALL<\/code> have signed 32-bit byte displacements; BRZ<\/code> and BRNZ<\/code> have signed 16-bit byte displacements.<\/p>\n\n\n\n
There is no CMP<\/code> instruction or condition-code register. Equality can be tested by subtracting or XORing two values and branching on the result:<\/p>\n\n\n\n
XOR R3, R1, R2\nBRZ R3, equal<\/code><\/pre>\n\n\n\n
CALL<\/code> does not push a return address onto the stack. Nested functions must preserve R31<\/code> explicitly; the initial C compiler does this for functions containing calls.<\/p>\n\n\n\n
The current ISA has no dedicated general-register indirect jump or indirect call. RET<\/code> provides register-directed control transfer specifically through R31<\/code>.<\/p>\n\n\n\n
An assembler detail matters here: a symbolic operand such as CALL function<\/code> resolves to a target address, but a numeric operand such as JMP 16<\/code> is interpreted as a relative displacement<\/strong>, not an absolute address.<\/p>\n\n\n\n
System and privilege instructions \u2014 6 instructions<\/strong><\/p>\n\n\n\n
Opcode<\/th>Instruction<\/th>Bytes<\/th>Operation<\/th><\/tr><\/thead>
50<\/code><\/td>SVC<\/code><\/td>1<\/td>Enter the Supervisor exception handler.<\/td><\/tr>
51<\/code><\/td>ERET<\/code><\/td>1<\/td>Return from an exception using saved status and PC.<\/td><\/tr>
52<\/code><\/td>WFI<\/code><\/td>1<\/td>Advance PC and wait for an interrupt.<\/td><\/tr>
53<\/code><\/td>MFSR Rd, csr8<\/code><\/td>3<\/td>Read a system register into a GPR.<\/td><\/tr>
54<\/code><\/td>MTSR csr8, Rs<\/code><\/td>3<\/td>Write a GPR value to a system register.<\/td><\/tr>
55<\/code><\/td>TLBINV<\/code><\/td>1<\/td>Invalidate all cached address translations.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
ERET<\/code>, MFSR<\/code>, MTSR<\/code>, and TLBINV<\/code> are Supervisor-only. The current emulator does not impose a Supervisor-only check on WFI<\/code>.<\/p>\n\n\n\n
SVC<\/code> has no immediate syscall-number operand. Selecting a service and passing arguments are responsibilities of the operating-system ABI.<\/p>\n\n\n\n
On exception entry, the processor:<\/p>\n\n\n\n
    \n
  1. Saves STATUS<\/code> in ESTATUS<\/code>.<\/li>\n\n\n\n
  2. Exchanges R30<\/code> and KSP<\/code> if entering from User mode.<\/li>\n\n\n\n
  3. Records the return\/restart address in EPC<\/code> and exception information in CAUSE<\/code> and BADADDR<\/code>.<\/li>\n\n\n\n
  4. Clears the User and interrupt-enable bits.<\/li>\n\n\n\n
  5. Transfers execution to EVEC<\/code>.<\/li>\n<\/ol>\n\n\n\n
    For SVC<\/code>, EPC<\/code> points to the next instruction. ERET<\/code> restores STATUS<\/code> from ESTATUS<\/code>, returns to EPC<\/code>, and reverses the stack exchange when returning to User mode.<\/p>\n\n\n\n
    WFI<\/code> allows device and timer activity to continue while the core is idle. An enabled pending interrupt wakes it.<\/p>\n\n\n\n
    TLBINV<\/code> currently flushes the entire TLB. Writing PTBR<\/code> or ASID<\/code> does not<\/strong> implicitly flush it.<\/p>\n\n\n\n
    System-register map<\/strong><\/p>\n\n\n\n
    The CSR selector is one byte, with these ten selectors implemented:<\/p>\n\n\n\n
    ID<\/th>Name<\/th>Meaning and behavior<\/th><\/tr><\/thead>
    0<\/code><\/td>STATUS<\/code><\/td>Current interrupt-enable, MMU-enable, and privilege bits.<\/td><\/tr>
    1<\/code><\/td>EVEC<\/code><\/td>Exception-handler entry address.<\/td><\/tr>
    2<\/code><\/td>EPC<\/code><\/td>Exception return\/restart address.<\/td><\/tr>
    3<\/code><\/td>CAUSE<\/code><\/td>Exception or interrupt cause.<\/td><\/tr>
    4<\/code><\/td>BADADDR<\/code><\/td>Address associated with a fault.<\/td><\/tr>
    5<\/code><\/td>PTBR<\/code><\/td>Physical page-table root address; low 12 bits are cleared on write.<\/td><\/tr>
    6<\/code><\/td>ASID<\/code><\/td>Address-space identifier used to tag translations.<\/td><\/tr>
    7<\/code><\/td>KSP<\/code><\/td>Stack-exchange register for User\/Supervisor transitions.<\/td><\/tr>
    8<\/code><\/td>ESTATUS<\/code><\/td>Saved status restored by ERET<\/code>.<\/td><\/tr>
    9<\/code><\/td>TICKS<\/code><\/td>Reference emulator cycle counter; writes are ignored.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
    STATUS<\/code> and ESTATUS<\/code> use:<\/p>\n\n\n\n
    Bit<\/th>Meaning<\/th><\/tr><\/thead>
    0<\/code><\/td>Interrupt enable<\/td><\/tr>
    1<\/code><\/td>MMU enable<\/td><\/tr>
    2<\/code><\/td>User mode<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
    Other bits are discarded on writes in the current implementation. Unsupported CSR selectors raise an illegal-instruction exception.<\/p>\n\n\n\n
    The assembler currently expects numeric CSR selectors:<\/p>\n\n\n\n
    MFSR R1, 0\nMTSR 5, R2\nTLBINV<\/code><\/pre>\n\n\n\n
    Execution and debugging \u2014 3 instructions<\/strong><\/p>\n\n\n\n
    Opcode<\/th>Instruction<\/th>Bytes<\/th>Operation<\/th><\/tr><\/thead>
    00<\/code><\/td>NOP<\/code><\/td>1<\/td>No operation.<\/td><\/tr>
    01<\/code><\/td>HALT<\/code><\/td>1<\/td>Stop the core; Supervisor-only.<\/td><\/tr>
    FF<\/code><\/td>BREAK<\/code><\/td>1<\/td>Debugger breakpoint operation.<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
    In the reference emulator, BREAK<\/code> sets the breakpoint indicator and halts execution. Although the ISA document describes it as a breakpoint trap, it does not currently enter the guest exception handler<\/strong>.<\/p>\n\n\n\n
    512-bit VLIW packet format<\/strong><\/p>\n\n\n\n
    Packetization adds a container and scheduling metadata, not another set of arithmetic instructions.<\/p>\n\n\n\n
    Every packet is exactly 64 bytes<\/strong>, starts at a 64-byte-aligned address, and contains an eight-byte header followed by up to 56 bytes of instruction payload.<\/p>\n\n\n\n
    Byte offset<\/th>Contents<\/th><\/tr><\/thead>
    0<\/code><\/td>Packet marker F0<\/code><\/td><\/tr>
    1<\/code>, bits 3\u20130<\/td>Format number; currently 0<\/code><\/td><\/tr>
    1<\/code>, bits 7\u20134<\/td>Number of active slots minus one<\/td><\/tr>
    2<\/code><\/td>Stop mask: bit n<\/em> places a stop after slot n<\/em><\/td><\/tr>
    3<\/code><\/td>Flags; must currently be zero<\/td><\/tr>
    4<\/code><\/td>Slot 0 length in low nibble; slot 1 length in high nibble<\/td><\/tr>
    5<\/code><\/td>Slot 2 and slot 3 lengths<\/td><\/tr>
    6<\/code><\/td>Slot 4 and slot 5 lengths<\/td><\/tr>
    7<\/code><\/td>Slot 6 and slot 7 lengths<\/td><\/tr>
    8\u201363<\/code><\/td>Scalar instructions followed by zero padding<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
    A packet contains one through eight instructions<\/strong>. The sum of their lengths must not exceed 56 bytes. Nested packets are illegal.<\/p>\n\n\n\n
    Stop bits divide the packet into issue groups<\/strong>. Every instruction within a group reads the register values present at the beginning of that group. Register results become visible at the group boundary. The last active slot always ends a group.<\/p>\n\n\n\n
    For example:<\/p>\n\n\n\n
    .packet\n    ADD R5, R1, R2\n    XOR R6, R3, R4\n.stop\n    MUL R7, R5, R6\n.endpacket<\/code><\/pre>\n\n\n\n
    The ADD<\/code> and XOR<\/code> can execute independently. The stop makes their results available to MUL<\/code>.<\/p>\n\n\n\n
    Without that stop, MUL<\/code> would read the old<\/strong> values of R5<\/code> and R6<\/code>. Two instructions in the same group may not write the same GPR.<\/p>\n\n\n\n
    Packetization does not guarantee eight operations per cycle. An implementation may execute a group serially or in parallel, provided it preserves the group\u2019s architectural semantics.<\/p>\n\n\n\n
    Current packet eligibility<\/strong><\/p>\n\n\n\n
    Instruction family<\/th>v0.13 reference emulator<\/th><\/tr><\/thead>
    NOP<\/code>, MOV<\/code>, MOVI<\/code><\/td>Supported<\/td><\/tr>
    All eight arithmetic\/logic instructions<\/td>Supported<\/td><\/tr>
    LD64<\/code>, LD8U<\/code>, LD16U<\/code>, LD32U<\/code><\/td>Supported<\/td><\/tr>
    ST64<\/code><\/td>Supported<\/td><\/tr>
    ST8<\/code>, ST16<\/code>, ST32<\/code><\/td>Rejected during packet execution<\/td><\/tr>
    Jumps, conditional branches, calls, returns<\/td>Prohibited<\/td><\/tr>
    All six system instructions<\/td>Prohibited<\/td><\/tr>
    HALT<\/code>, BREAK<\/code><\/td>Prohibited<\/td><\/tr><\/tbody><\/table><\/figure>\n\n\n\n
    There are two material implementation gaps:<\/p>\n\n\n\n